AT91SAM9261_14 Datasheet, PDF (215/749 Pages) ATMEL Corporation – DSP Instruction Extensions

AT91SAM9261
22.6.2 SDRAMC Refresh Timer Register
Register: SDRAMC_TR
Address: 0xFFFFEA04
Access Type:Read-write
Reset Value: 0x00000000
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
COUNT
7
6
5
4
3
2
1
0
COUNT
• COUNT: SDRAMC Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh
burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate
of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of length one.
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is
issued and no refresh of the SDRAM device is carried out.
6062N–ATARM–3-Oct-11
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