ATMEGA169V Datasheet, PDF (211/365 Pages) ATMEL Corporation – 8-bit Microcontroller with 16K Bytes In-System Programmable Flash

LCD Clock Sources
LCD Prescaler
LCD Memory
2514P–AVR–07/06
ATmega169/V
Figure 97. LCD Module Block Diagram
clk_i/o
0
TOSC
1
clk_LCD
lcdcs
12-bit Prescaler
LCDFRR
lcdps2:0
Clock
Multiplexer
LCDCRA
lcdcd2:0
Divide by 1 to 8
LCDCRB
clk_{LCD_PS}
D
A
T
A
LCDDR 18 -15
LCD
Timing
B
U
S
LCDDR 13 -10
LCDDR 8 - 5
LATCH
array
25 x
4:1
MUX
LCD Ouput
Decoder
Analog
Switch
Array
LCDDR 3 - 0
Display
Configuration
LCD_voltage_ok
LCD Buffer/
Driver
1/3 V_LCD
1/2 V_LCD
2/3 V_LCD
LCDCCR
lcdcc3:0
Contrast Controller/
Power Supply
LCD
CAP
V_LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
The LCD Controller can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clk_LCD is by default equal to the system clock, clk_I/O.
When the LCDCS bit in the LCDCRB Register is written to logic one, the clock source is
taken from the TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC
voltage offset across LCD segments.
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The
LCDPS2:0 bits selects clk_LCD divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock
further by 1 to 8.
Output from the clock divider clk_{LCD_PS} is used as clock source for the LCD timing.
The display memory is available through I/O Registers grouped for each common termi-
nal. When a bit in the display memory is written to one, the corresponding segment is
energized (on), and non-energized when a bit in the display memory is written to zero.
To energize a segment, an absolute voltage above a certain threshold must be applied.
This is done by letting the output voltage on corresponding COM pin and SEG pin have
opposite phase. For display with more than one common, one (1/2 bias) or two (1/3
bias) additional voltage levels must be applied. Otherwise, non-energized segments on
COM0 would be energized for all non-selected common.
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