ATA5278 Datasheet, PDF (21/33 Pages) ATMEL Corporation – STAND-ALONE ANTENNA DRIVER

ATA5278 [Preliminary]
Figure 17. Fault Shutdown Timing
t < t_deb,min
Internal fault
signal
Driver output
stage
X
Boost converter
operation
QSC gate
signal
MODACTIVE pin
t > t_deb,min
1
X
1
1
1
Fault is latched in status
register afterwards
Z
0
0
0
Note: Internal fault signal rises as soon as a fault (overtemperature, short-circuit or open load) is detected
Figure 17 shows the sequence of a fault shutdown during the antenna driver-stage
being active. If a critical condition persists for a time shorter than the debouncing time
(e.g., caused by interferences), no shutdown will occur.
The diagnosis bits are based in the status register and are encoded as shown in Table
4.
Table 4. Diagnosis Bits (Status Register)
Bit Position Bit Name Fault Type
0 (LSB)
OT
Overtemperature detected
1
SL
Antenna driver output pin has overload to Ground
2
SH
Antenna driver output pin has overload to VDS (VBATT)
3
OL
Open load detected (no oscillation at VSHUNT pin)
4
CH
Overcurrent at antenna return line (QSC drain input) detected
5
IC
Illegal command in the SPI input register found
6
-
Not defined
7 (MSB)
-
Not defined
CLKO Output Pin
The clock output pin CLKO of the ATA5278 can be used to supply an on-board micro-
controller with a clock signal (either 4 MHz or 8 MHz). This signal is not suited to supply
any device beyond the PCB boundaries.
The clock signal is directly derived from the clock source connected to the OSCI/OSCO
pins of the ATA5278 and is available as long as the ATA5278 is not in power-down
mode. The frequency can be selected with the prescaler (PS) bit in configuration
register 2, which is 0 for the full-clock rate (f_CLKO = f_OSCI) or 1 for the half clock-rate
(f_CLKO = f_OSCI/2).
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4832A–RKE–10/04