ATMEGA165P Datasheet, PDF (209/365 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash

ATmega165P
20.2.3
Input Capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the Input Capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in Table 20-2 on page 209.
Table 20-2.
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ACIS0
Interrupt Mode
0
Comparator Interrupt on Output Toggle.
1
Reserved
0
Comparator Interrupt on Falling Output Edge.
1
Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
DIDR1 – Digital Input Disable Register 1
Bit
7
6
5
4
3
2
1
0
(0x7F)
–
–
–
–
–
–
AIN1D
AIN0D
DIDR1
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
8018A–AVR–03/06
209