AT90USB646_0607 Datasheet, PDF (208/435 Pages) ATMEL Corporation – 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller

Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
f_osc = 16.0000 MHz
U2Xn = 0
U2Xn = 1
UBRR Error UBRR Error
f_osc = 18.4320 MHz
U2Xn = 0
U2Xn = 1
UBRR Error UBRR Error
f_osc = 20.0000 MHz
U2Xn = 0
U2Xn = 1
UBRR Error UBRR Error
2400
416 -0.1%
832
0.0%
479
0.0%
959
0.0%
520
0.0% 1041 0.0%
4800
207
0.2%
416
-0.1% 239
0.0%
479
0.0%
259
0.2%
520
0.0%
9600
103
0.2%
207
0.2%
119
0.0%
239
0.0%
129
0.2%
259
0.2%
14.4k
68
0.6%
138 -0.1%
79
0.0%
159
0.0%
86
-0.2% 173 -0.2%
19.2k
51
0.2%
103
0.2%
59
0.0%
119
0.0%
64
0.2%
129
0.2%
28.8k
34
-0.8%
68
0.6%
39
0.0%
79
0.0%
42
0.9%
86
-0.2%
38.4k
25
0.2%
51
0.2%
29
0.0%
59
0.0%
32
-1.4%
64
0.2%
57.6k
16
2.1%
34
-0.8%
19
0.0%
39
0.0%
21
-1.4%
42
0.9%
76.8k
12
0.2%
25
0.2%
14
0.0%
29
0.0%
15
1.7%
32
-1.4%
115.2k
8
-3.5%
16
2.1%
9
0.0%
19
0.0%
10
-1.4%
21
-1.4%
230.4k
3
8.5%
8
-3.5%
4
0.0%
9
0.0%
4
8.5%
10
-1.4%
250k
3
0.0%
7
0.0%
4
-7.8%
8
2.4%
4
0.0%
9
0.0%
0.5M
1
0.0%
3
0.0%
–
–
4
-7.8%
–
–
4
0.0%
1M
Max. ⁽¹⁾
0
0.0%
1 Mbps
1
0.0%
2 Mbps
–
–
1.152 Mbps
–
–
2.304 Mbps
–
–
1.25 Mbps
–
–
2.5 Mbps
1.
UBRR = 0, Error = 0.0%
19. USART in SPI Mode
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-
ing features:
• Full Duplex, Three-wire Synchronous Data Transfer
• Master Operation
• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
• LSB First or MSB First Data Transfer (Configurable Data Order)
• Queued Operation (Double Buffered)
• High Resolution Baud Rate Generator
• High Speed Operation (fXCKmax = fCK/2)
• Flexible Interrupt Generation
19.1 Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
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