ATMEGA644_0702 Datasheet, PDF (206/374 Pages) ATMEL Corporation – 8-bit Microcontroller with 64K Bytes In- System Programmable Flash

19.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 19-9. All registers
drawn in a thick line are accessible through the AVR data bus.
Figure 19-9. Overview of the TWI Module
SCL
Slew-rate
Control
Spike
Filter
SDA
Slew-rate Spike
Control
Filter
Bus Interface Unit
START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Ack
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Address Match Unit
Address Register
(TWAR)
Address Comparator
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
19.5.1
19.5.2
SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
206 ATmega644
2593L–AVR–02/07