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AT85C51SND3B Datasheet, PDF (204/270 Pages) ATMEL Corporation – Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface
Bit
Bit
Number Mnemonic Description
Data Transfer Enable Bit
Set to enable data transmission or reception immediately or after response has
2
DATEN been received.
Cleared by hardware after the CRC reception in reception mode or after the busy
status if any in transmission mode.
Response Command Enable Bit
1
RXCEN Set to enable the reception of a response following a command transmission.
Cleared by hardware when response is received.
Command Transmission Enable Bit
0
TXCEN Set to enable transmission of the command FIFO to the card.
Cleared by hardware when command is transmitted.
Reset Value = 0000 0000b
Table 224. MMCON2 Register
MMCON2 (1.B3h) – MMC Control Register 2
7
6
5
4
3
FCK
DCR
CCR
DBSIZE1 DBSIZE0
2
DATD1
1
DATD0
0
MMCEN
Bit
Number
7
6
5
4-3
2-1
0
Bit
Mnemonic Description
FCK
MMC Force Clock Bit
Set to enable the MCLK clock out permanently.
Clear to disable the MCLK clock and enable flow control.
DCR
Data Controller Reset Bit
Set to reset the data line controller in case of transfer abort, or to reset CRC16S
bit after an error occurs.
Cleared by hardware after the data line controller reset is achieved.
CCR
Command Controller Reset Bit
Set to reset the command line controller in case of transfer abort.
Cleared by hardware after the command line controller reset is achieved.
Data Bus Size
DBSIZE1:0
Refer to Table 220 for bits description.
DATD1:0
Data Transmission Delay Bits
Used to delay the data transmission after a response from 3 MMC clock periods
(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock
periods.
MMCEN
MMC Clock Enable Bit
Set to enable the MMC clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Reset Value = 0000 0000b
Table 225. MMBLP Register
MMCON2 (1.B4h) – MMC Block Length LSB Register
7
6
5
4
3
BLEN7
BLEN6
BLEN5
BLEN4
BLEN3
2
BLEN2
1
BLEN1
0
BLEN0
204 AT85C51SND3B
7632C–MP3–11/06