ATA5749_14 Datasheet, PDF (20/26 Pages) ATMEL Corporation – Fractional-N PLL Transmitter IC

10. Electrical Characteristics (Continued)
V_S = 1.9V to 3.6V T_amb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10pF. f_XTO = 13.0000MHz,
f_CLK = 1.625MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with C_M = 4.0fF,
C₀ = 1.5pF, C_LOAD = 9pF and R_M ≤ 170Ω. Typical values are given at V_S = 3.0V and T_amb = 25°C
No. Parameters
Test Conditions
Pin Symbol Min. Typ. Max. Unit Type*
3.5
DC voltage after XTAL
amplitude stable
V(XTO2) – V(XTO1)
XTO running
6, 7
V_{DC_XTO}
40
mV
C
This value is important for crystal
Negative real part of
3.6 XTO impedance at
begin of start-up
oscillator start-up behavior
C₀ < 2.0pF,
8pF < C_LOAD < 10pF
F_XTAL = 13.000MHz
11.0MHz < F_XTAL < 14.8MHz
6, 7 R_{XTO12_START} ^–1,500 –2,200
–1,300
Ω
B
Recommended values for
proper start-up and low current
consumption
3.7
External capacitors
C4, C5
Quality NPO
C_LOAD = (C₄ + C_XTO1) ×
(C₅ + C_XTO2) /
(C₄ + C₅ + C_XTO1 + C_XTO2)
C_{Load_nom} = 9pF (inc. PCB)
6, 7
C₄
C₅
–5%
15
+5%
pF
D
3.8
Pin capacitance
XTO1 and XTO2
The PCB capacitance of about
1pF has to be added
6, 7
C_XTO1
C_XTO2
–15%
–15%
2
2
+15%
+15%
pF
C
Time between EN = “High” and
XTO_RDY = “High”
3.9
Crystal oscillator start-
up time
C₀ < 2.0pF, 4fF < C_M < 15fF
C₀ < 2.0pF, 2fF < C_M < 15fF
R_M < 170Ω
11.0MHz < F_XTAL < 14.8MHz
6, 7, 1 ΔT_XTO
0.20
0.3
0.32
0.5
ms
B
3.10
Maximum shunt
Required for stable operation of
capacitance C₀ of XTAL XTO, C_Load > 7. 5pF
6, 7
C_{0_MAX}
1.5
3.0
pF
D
3.11
Oscillator frequency
XTO
433.92MHz and 315MHz other
frequencies
6, 7
f_XTO
13.0000
11.0
14.8
MHz
C
4 Fractional-N-PLL
4.1
Frequency range of RF S434_N315 = “LOW”
frequency
S434_N315 = “HIGH”
5
f_RF
300
367
368
450
MHz
A
Time between
XTO_RDY= “High” and Register
98.46 µs
B
4.2 Locking time of the PLL programmed till PLL is locked 1, 5
f_XTO = 13.0000MHz
other f_XTO
ΔT_PLL


1f2_X8_T0_O/_
4.3 PLL loop bandwidth
Unity gain loop frequency of
synthesizer
5
f_{Loop_PLL}
140
280
380
kHz
B
4.4 In loop phase noise PLL 25kHz distance to carrier
4.5
Out of loop phase noise At 1MHz
(VCO)
At 36MHz
5
L_PLL
5
L_at1M
L_at36M
–83
–76 dBc/Hz A
–91
–84 dBc/Hz ^A
–122 –115 dBc/Hz _C
4.6
FSK modulation
frequency
Duty cycle of the modulation
signal = 50%, (this corresponds
to 40kBit/s Manchester coding
2, 5
F_{MOD_FSK}
0
and 80kBit/s NRZ coding)
40
kHz
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component
values and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
20 ATA5749/ATA5749C [DATASHEET]
9128I–RKE–04/14