AT91CAP7L200A Datasheet, PDF (20/47 Pages) ATMEL Corporation – Customizable Microcontroller

7. Processor and Architecture
7.1 ARM7TDMI Processor
• RISC Processor Based on ARMv4T Von Neumann Architecture
– Runs at up to 80 MHz, providing up to 72 MIPS
• Two instruction sets
– ARM high-performance 32-bit Instruction Set
– Thumb high code density 16-bit Instruction Set
• Three-stage pipeline architecture
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
7.2 Debug and Test Features
• Integrated embedded in-circuit emulator
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
• Debug Unit
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID and EXTended Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on all digital pins, except reset, backup reset, and test pins
7.3 Bus Matrix
• 6 Layers Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
20 AT91CAP7L200A [Preliminary]
8685AS–CAP–05/09