AT90LS2323_14 Datasheet, PDF (20/64 Pages) ATMEL Corporation – AVR – High-performance and Low-power RISC Architecture

Reset Sources
The most typical program setup for the Reset and Interrupt vector addresses are:
Address
$000
$001
$002
$003
...
Labels
MAIN:
...
Code
rjmp RESET
rjmp EXT_INT0
rjmp TIM_OVF0
ldi r16, low(RAMEND)
out SPL, r16
<instr> xxx
...
Comments
; Reset Handler
; IRQ0 Handler
; Timer0 Overflow
; Handler;
; Main program start
...
The AT90S2323/2343 provides three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V_POT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
During reset, all I/O registers are set to their initial values and the program starts execu-
tion from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the interrupt vectors are not used and regular program code can be
placed at these locations. The circuit diagram in Figure 24 shows the reset logic.
Table 4 defines the timing and electrical parameters of the reset circuitry.
Figure 24. Reset Logic
VCC
Power-On Reset
Circuit
100 - 500K
RESET
Reset Circuit
POR
S
Q
Watchdog
Timer
On-Chip
RC-Oscillator
14-Stage Ripple Counter
Q0
Q3
Q13
R
Q
The AT90S/LS2323 has a programmable start-up time. A fuse bit (FSTRT) in the Flash
memory selects the shortest start-up time when programmed (“0”). The AT90S/LS2323
is shipped with this bit unprogrammed.
The AT90S/LS2343 has a fixed start-up time.
20 AT90S/LS2323/2343
1004D–09/01