AT25DF321_09 Datasheet, PDF (20/37 Pages) ATMEL Corporation – 32-megabit 2.7-volt Minimum SPI Serial Flash Memory

10. Status Register Commands
10.1
Read Status Register
The Status Register can be read to determine the device’s ready/busy status, as well as the sta-
tus of many other functions such as Hardware Locking and Software Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the last bit of the opcode has been clocked in, the device will begin
outputting Status Register data on the SO pin during every subsequent clock cycle. After the last
bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting
again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The
data in the Status Register is constantly being updated, so each repeating sequence will output
new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
Table 10-1. Status Register Format
Bit⁽¹⁾
Name
Type⁽²⁾ Description
0 Sector Protection Registers are unlocked (default).
7
SPRL Sector Protection Registers Locked R/W
1 Sector Protection Registers are locked.
6
RES Reserved for future use
R
0 Reserved for future use.
5
EPE Erase/Program Error
0 Erase or program operation was successful.
R
1 Erase or program error detected.
4
WPP Write Protect (WP) Pin Status
0 WP is asserted.
R
1 WP is deasserted.
00
All sectors are software unprotected (all Sector
Protection Registers are 0).
3:2
SWP Software Protection Status
Some sectors are software protected. Read individual
01 Sector Protection Registers to determine which
R
sectors are protected.
10 Reserved for future use.
11
All sectors are software protected (all Sector
Protection Registers are 1 – default).
1
WEL Write Enable Latch Status
0 Device is not write enabled (default).
R
1 Device is write enabled.
0
Notes:
RDY/BS
Y
Ready/Busy Status
0 Device is ready.
R
1 Device is busy with an internal operation.
1. Only bit 7 of the Status Register will be modified when using the Write Status Register command.
2. R/W = Readable and writeable
R = Readable only
20 AT25DF321
3669B–DFLASH–6/09