ATTINY44_14 Datasheet, PDF (2/238 Pages) ATMEL Corporation – Non-Volatile Program and Data Memories

1. Pin Configurations
Figure 1-1. Pinout ATtiny24/44/84
PDIP/SOIC
VCC 1
(PCINT8/XTAL1/CLKI) PB0 2
(PCINT9/XTAL2) PB1 3
(PCINT11/RESET/dW) PB3 4
(PCINT10/INT0/OC0A/CKOUT) PB2 5
(PCINT7/ICP/OC0B/ADC7) PA7 6
(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 7
14 GND
13 PA0 (ADC0/AREF/PCINT0)
12 PA1 (ADC1/AIN0/PCINT1)
11 PA2 (ADC2/AIN1/PCINT2)
10 PA3 (ADC3/T0/PCINT3)
9 PA4 (ADC4/USCK/SCL/T1/PCINT4)
8 PA5 (ADC5/DO/MISO/OC1B/PCINT5)
QFN/MLF
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
(ADC4/USCK/SCL/T1/PCINT4) PA4 1
(ADC3/T0/PCINT3) PA3 2
(ADC2/AIN1/PCINT2) PA2 3
(ADC1/AIN0/PCINT1) PA1 4
(ADC0/AREF/PCINT0) PA0 5
15 PA7 (PCINT7/ICP/OC0B/ADC7)
14 PB2 (PCINT10/INT0/OC0A/CKOUT)
13 PB3 (PCINT11/RESET/dW)
12 PB1 (PCINT9/XTAL2)
11 PB0 (PCINT8/XTAL1/CLKI)
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
2 ATtiny24/44/84
8006K–AVR–10/10