AT49BV8192A-11TI Datasheet, PDF (2/16 Pages) ATMEL Corporation – 8-megabit (1M x 8/512K x 6) Flash memory

AT49BV8192A(T) TSOP Top View
Type 1
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE 11
RESET 12
VPP 13
NC 14
NC 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
48 A16
47 BYTE
46 GND
45 I/O15 / A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
AT49BV8192A(T) SOIC (SOP) Top View
VPP 1
A18 2
A17 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
CE 12
GND 13
OE 14
I/O0 15
I/O8 16
I/O1 17
I/O9 18
I/O2 19
I/O10 20
I/O3 21
I/O11 22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 GND
31 I/O15
30 I/O7
29 I/O14
28 I/O6
27 I/O13
26 I/O5
25 I/O12
24 I/O4
23 VCC
AT49BV008A(T) TSOP Top View
Type 1
A16 1
A15 2
A14 3
A13 4
A12 5
A11 6
A9 7
A8 8
WE 9
RESET 10
VPP 11
RDY/BUSY 12
A18 13
A7 14
A6 15
A5 16
A4 17
A3 18
A2 19
A1 20
40 A17
39 GND
38 NC
37 A-1
36 A10
35 I/O7
34 I/O6
33 I/O5
32 I/O4
31 VCC
30 VCC
29 NC
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 OE
23 GND
22 CE
21 A0
AT49BV8192A(T)
CBGA Top View (Ball Down)
12345678
A
A13 A11 A8 VPP NC NC A7 A4
B
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9 NC NC A6 A3 A1
D
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0
E
BYTE I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
F
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
AT49BV008A(T) Standard Pin Definition
CBGA Top View (Ball Down)
12345678
A
A13 A11 A8 VPP NC NC A7 A4
B
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9 NC NC A6 A3 A1
D
A16 NC I/O5 NC I/O2 NC CE A0
E
NC A-1 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
Note: “•” denotes a white dot on the package.
AT49BV008A(T) Alternate Pin Definition
CBGA Top View (Ball Down)
12345678
A
A14 A12 A8 VPP NC NC A7 A4
B
A15 A10 WE RST A19 A18 A5 A2
C
A16 A13 A9 NC NC A6 A3 A1
D
A17 NC I/O5 NC I/O2 NC CE A0
E
NC A11 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
bus contention. Reprogramming the AT49BV008A(T)/
8192A(T) is performed by first erasing a block of data and
then by programming on a byte-by-byte or word-by-word
basis.
The device is erased by executing the Erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typi-
cal number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. This
feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in
the boot block cannot be changed when input levels of 5.5
volts or less are used. The boot sector is designed to con-
tain user secure code.
For the AT49BV8192A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
2 AT49BV008A(T)/8192A(T)