AT49BV1604 Datasheet, PDF (2/18 Pages) ATMEL Corporation – 16-Megabit 1M x 16/2M x 8 3-volt Only Flash Memory

A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE 11
RESET 12
VPP 13
NC 14
A19 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
TSOP Top View
Type 1
48 A16
47 VCCQ
46 GND
45 I/O15
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
AT49BV1604(T)
µBGA Top View (Ball Down)
1 2 3 4 5 6 78
A
A13 A11 A8 VPP NC A19 A7 A4
B
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9 NC NC A6 A3 A1
D
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0
E
VCCQ I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
F
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
TSOP Top View
Type 1
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A19 9
NC 10
WE 11
RESET 12
VPP 13
NC 14
RDY/BUSY 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
48 A16
47 BYTE
46 GND
45 I/O15/A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
AT49BV1614(T)
CBGA Top View
HGF EDCBA
1
VSS OE CE A0 A1 A2 A4 A3
2
I/O1 I/O9 I/O8 I/O0 A5 A6 A17 A7
3
I/O3 I/O11 I/O10 I/O2 NC A18 NC RDY/BUSY
4
I/O4 VCC I/O12 I/O5 A19 NC RESET WE
5
I/O6 I/O13 I/O14 I/O7 A11 A10 A8 A9
6
VSS I/O15 BYTE A16 A15 A14 A12 A13
/A-1
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and V_CC.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
A V_PP pin is provided to improve program/erase times at
lower supply voltages. This pin does not need to be uti-
lized. If it is not used the pin should be connected to ground
or V_CC. To take advantage of faster programming, the pin
should supply 5.0 volts during program and erase opera-
tions.
2
AT49BV16X4(T)