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| AT27C040-90PU Datasheet, PDF (2/13 Pages) ATMEL Corporation – 4Mb (512K x 8) OTP, EPROM | |||
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2. Pin Configurations and Pinouts
Pin
Name
VPP
A0 - A18
O0 - O7
GND
CE
OE
VCC
Function
Peak to Peak Voltage
Address Inputs
Outputs
Ground
Chip Enable
Output Enable
Device Power Supply
32-lead PLCC
Top view
32-lead PDIP
Top view
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
O0 13
VPP 1
A16 2
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
A15 3
A12 4
A7 5
A6 6
A5 7
A4 8
23 A10
22 CE
A3 9
A2 10
21 O7
A1 11
A0 12
O0 13
O1 14
O2 15
GND 16
32 VCC
31 A18
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 O7
20 O6
19 O5
18 O4
17 O3
3. Switching Considerations
Switching between active and standby conditions via the Chip Enable (CE) pin may produce transient voltage
excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in
device nonconformance. At a minimum, a 0.1μF, high-frequency, low inherent inductance, ceramic capacitor should be
utilized for each device. This capacitor should be connected between the VCC and ground terminals of the device â as
close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7μF bulk electrolytic capacitor should be utilized, again connected between the VCC and ground
terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to
the array.
4. Block Diagram
VCC
GND
VPP
OE
CE
A0 â A18
Address
Inputs
OE, CE, and
Program Logic
Y Decoder
X Decoder
Data Outputs
O0 â O7
Output
Buffers
Y-Gating
Cell Matrix
Identification
Atmel AT27C040 [DATASHEET]
2
0189JâEPROMâ10/2012
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