M44C090-H Datasheet, PDF (19/63 Pages) ATMEL Corporation – Low-Current Microcontroller for Wireless Communication

M44C090-H
M44C890-H
3 Peripheral Modules
3.1 Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 21). The IN or OUT instructions allow di-
rect addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted to enable direct ad-
dressing of the ”primary register”. To address the
”auxiliary register”, the access must be switched with an
”auxiliary switching module”. Thus a single IN (or OUT)
to the module address will read (or write) into the module
primary register. Accessing the auxiliary register is per-
formed with the same instruction preceded by writing the
module address into the auxiliary switching module. Byte
wide registers are accessed by multiple IN- (or OUT-)
instructions. For more complex peripheral modules, with
a larger number of registers, extended addressing is used.
In this case a bank of up to 16 subport registers are indi-
rectly addressed with the subport address. The first
OUT-instruction writes the subport address to the sub-
address register, the second IN- or OUT-instruction reads
data from or writes data to the addressed subport.
Module ASW
Module M1
(Address Pointer)
Subaddress Reg.
Bank of
Primary Regs.
Module M2
Aux. Reg.
Module M3
Auxiliary Switch
Subport Fh
Mo d ule
5
1
Subport Eh
Primary Reg.
Subport 1
Subport 0
2
4
I/O bus
Primary Reg.
3
Primary Reg.
6
to other modules
Example of
qF ORTH
Pr ogra m
Code
Indirect Subport
Access
(Subport Register Write)
1 _{Addr.(SPort) Addr.(M1) OUT}
2 SPort_Data Addr.(M1) OUT
(Subport Register Read)
1 Addr.(SPort) Addr.(M1) OUT
2
Addr.(M1) IN
(Subport Register Write Byte)
1 Addr.(SPort) Addr.(M1) OUT
2 SPort_Data(lo) Addr.(M1) OUT
2 SPort_Data(hi) Addr.(M1) OUT
(Subport Register Rea d Byte)
1 Addr.(SPort) Addr.(M1) OUT
2
Addr.(M 1) IN (hi)
2
Addr.(M 1) IN (lo)
Dual Register
Access
(Primary Register Write)
3 _{Prim._Data Address(M2) OU T}
( Auxiliary Register Write )
4 _{Address(M2) Address(ASW) OUT}
5 _{Aux._Data Address(M2) OUT}
Single Register
Access
(Prima ry Register Write)
6 _{Prim._Data Address(M3) O UT}
(Prima ry Register Read)
6
Address(M3) IN
(Primary Register Rea d)
3
Address(M2) IN
(Auxiliary Register Rea d)
4 ^{Address(M2) Address(ASW) OUT}
Address(M2) IN
5
(Auxiliary Register Write Byte)
4 _{Address(M2) Address(ASW) OUT}
5 _{Aux._Data(lo) Address(M2) OUT}
5 _{Aux._Data(hi) Address(M2) OUT}
Addr.(ASW) = Auxiliary Switch Module Address
Addr.(Mx) = Module Mx Addr ess
Addr.(SPort) = Subport Address
Prim._Data = data to be written into Primar y Register.
Aux._Data = da ta to be written into Auxilia ry Register
Aux._Data (lo)= data to be written into Auxiliary Register (low nibble)
Aux._Data (hi) = da ta to be written into Auxiliar y Register (high nibble)
SPort_Data(lo) = data to be written into SubP ort (low nibble)
SPort_Data(hi) = da ta to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
13357
Figure 21. Example of I/O addressing
Rev.A3, 14-Dec-01
19 (63)