AT91SAM9G46 Datasheet, PDF (19/59 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM9G46
Table 6-4. AT91SAM9G46 Masters to Slaves Access with DDRMP_DIS = 1 (default)
Master
0
1
2
3
4&5
6
7
8
9
10
11
Slave
ARM
ARM
926 Instr. 926 Data
PDC
USB
HOST
OHCI
DMA
ISI
DMA
LCD _{Ethernet USB USB Host}
DMA
MAC Device HS EHCI Reserved
0 Internal SRAM 0
X
X
X
X
X
X
-
X
X
X
-
Internal ROM
X
X
X
-
-
-
-
-
X
-
-
UHP OHCI
X
X
-
-
-
-
-
-
-
-
-
UHP EHCI
X
X
-
-
-
-
-
-
-
-
-
1
LCD User Int.
X
X
-
-
-
-
-
-
-
-
-
UDPHS RAM
X
X
-
-
-
-
-
-
-
-
-
Reserved
X
X
-
-
-
-
-
-
-
-
-
2
DDR Port 0
-
-
-
-
-
-
-
-
-
-
X
3
DDR Port 1
-
-
-
-
-
-
X
-
-
-
-
4
DDR Port 2
X
-
X
X
X
X
-
X
X
X
-
5
DDR Port 3
-
X
X
X
X
X
-
X
X
X
-
6
EBI
X
X
X
X
X
X
X
X
X
X
X
7
Internal Periph.
X
X
X
-
X
-
-
-
-
-
-
Table 6-5 summarizes the Slave Memory Mapping for each connected Master, depending on
the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and
the BMS state at reset.
Table 6-5. Internal Memory Mapping
Master
Slave
Base Address
RCBx = 0
BMS = 1
BMS = 0
0x0000 0000
Internal ROM
EBI NCS0
RCBx = 1
Internal SRAM
6.3 Peripheral DMA Controller (PDC)
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer support, prevents strong real-time constraints on buffer management.
19
11028BS–ATARM–26-Apr-10