ATMEGA168PA_14 Datasheet, PDF (185/326 Pages) ATMEL Corporation – ATMEL 8-BIT MICROCONTROLLER WITH 4/8/16/32KBYTES

22.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An
empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line
can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs
extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL
high period, which is determined by the Master. As a consequence, the Slave can reduce the TWI data transfer speed by
prolonging the SCL duty cycle.
Figure 22-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and
the STOP condition, depending on the software protocol implemented by the application software.
Figure 22-6. Typical Data Transmission
SDA
Addr MSB
Addr LSB R/W
ACK
Data MSB
Data LSB ACK
SCL
START
1
2
7
8
9
SLA + R/W
1
2
7
8
9
Data Byte
STOP
22.4
Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that
transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems
arise in multi-master systems:
● An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters
should cease transmission when they discover that they have lost the selection process. This selection process is
called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately
switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters
have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on
the bus must not be corrupted.
● Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks
from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration
process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-
ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low
period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen
to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high
or low, respectively.
ATmega48PA/88PA/168PA [DATASHEET] 185
9223F–AVR–04/14