ATMEGA169PA_1 Datasheet, PDF (183/387 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega169PA
19.7.5
19.7.6
19.7.7
Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1n) bit is set. Type of Par-
ity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software
to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPM1n = 1). This bit is
valid until the receive buffer (UDRn) is read.
Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will
no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Assembly Code Example⁽¹⁾
USART_Flush:
sbis UCSR0A, RXC0
ret
in r16, UDR0
rjmp USART_Flush
C Code Example⁽¹⁾
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSR0A & (1<<RXC0) ) dummy = UDR0;
}
Note: 1. See ”About Code Examples” on page 10.
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