ATMEGA48_09 Datasheet, PDF (181/340 Pages) ATMEL Corporation – 8-bit Microcontroller with 8K Bytes In-System Programmable Flash

ATmega48/88/168 Automotive
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 17-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit
of the next frame.
Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling
RxD
STOP 1 (A)
(B)
(C)
Sample
(U2X = 0)
Sample
(U2X = 1)
1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
1
2
3
4
5
6
0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 17-7. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
17.7.3
Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 17-2) base frequency, the Receiver will not be able to synchronize the frames to the start
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
Table 1.
R_slow
=
------------⁽---^D------+----¹----⁾---^S-------------
S – 1 + D ⋅ S + S_F
R_fast
=
-------⁽---^D------+----²----⁾---^S--------
(D + 1)S + S_M
D
Sum of character size and parity size (D = 5 to 10 bit)
S
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
S_F
First sample number used for majority voting. S_F = 8 for normal speed and S_F = 4
for Double Speed mode.
7530H–AVR–02/09
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