ATSAM9708_06 Datasheet, PDF (18/31 Pages) ATMEL Corporation – 128-voice Integrated Sound Synthesizer

Figure 13-3. Refresh Cycle (RAS Only)
t_RC
t_RAS
t_RP
RAS
(1)
DRA[11:0]
t_ASR
counter
t_RAH
Note: 1. See Table 12-1 on page 16.
Table 13-1.
Symbol
t_RC
t_RAC
t_CAC
t_OFF
t_RP
t_RAS
t_CAS
t_RCD
t_CRP
t_ASR
t_RAH
t_ASC
t_CAH
t_WCS
t_WCH
t_DS
t_DH
External DRAM Timing Parameters
Parameter
Read/Write/Refresh cycle
Access time from RAS
Access time from CAS
CAS high to output Hi-Z
RAS precharge time
RAS pulse width
CAS pulse width
RAS to CAS delay time
CAS to RAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Write command set-up time
Write command hold time
Write data set-up time
Write data hold time
Refresh counter average period
(12-bit counter)
Min
2 x t_CK
4 x t_CK - 5
3 x t_CK - 5
2 x t_CK - 5
t_CK - 5
t_CK - 5
t_CK - 5
3 x t_CK - 5
Typ
6 x t_CK
2 x t_CK
2 x t_CK
3 x t_CK
2 x t_CK
3 x t_CK
512 x t_CK
Max
5 x t_CK - 5
3 x t_CK - 5
2 x t_CK - 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The following points should be noted:
• The multiplexed CAS, RAS addressing can support memory DRAM chips up to 16 Mbits x N as long as the number of
row address lines and column address lines are identical. For example, device type 416C1200 is supported because it
is a 1M x 16 organization with 10-bit row and 10-bit column. Device type 416C1000 is not supported because it is a 1M
x 16 organization with 12-bit row and 8-bit column.
• The signal WOE is normally not used for DRAM connection. It is represented only for reference purposes.
18 ATSAM9708
1772E–DRMSD–10-Apr-06