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AT91SAM9XE128 Datasheet, PDF (18/50 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers | |||
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7. Processor and Architecture
7.1 ARM926EJ-S Processor
⢠RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
⢠Two Instruction Sets
â ARM High-performance 32-bit Instruction Set
â Thumb High Code Density 16-bit Instruction Set
⢠DSP Instruction Extensions
⢠5-Stage Pipeline Architecture:
â Instruction Fetch (F)
â Instruction Decode (D)
â Execute (E)
â Data Memory (M)
â Register Write (W)
⢠8 KB Data Cache, 16 KB Instruction Cache
â Virtually-addressed 4-way Associative Cache
â Eight words per line
â Write-through and Write-back Operation
â Pseudo-random or Round-robin Replacement
⢠Write Buffer
â Main Write Buffer with 16-word Data Buffer and 4-address Buffer
â DCache Write-back Buffer with 8-word Entries and a Single Address Entry
â Software Control Drain
⢠Standard ARM v4 and v5 Memory Management Unit (MMU)
â Access Permission for Sections
â Access Permission for large pages and small pages can be specified separately for
each quarter of the page
â 16 embedded domains
⢠Bus Interface Unit (BIU)
â Arbitrates and Schedules AHB Requests
â Separate Masters for both instruction and data access providing complete Matrix
system flexibility
â Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
â On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2 Bus Matrix
⢠6-layer Matrix, handling requests from 6 masters
⢠Programmable Arbitration strategy
â Fixed-priority Arbitration
18 AT91SAM9XE128/256/512 Preliminary
6254ASâATARMâ14-Feb-08
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