ATA8742 Datasheet, PDF (170/238 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

Table 25-6. ADC Prescaler Selections (Continued)
ADPS2
ADPS1
ADPS0
1
0
1
1
1
0
1
1
1
25.10.3 ADCL and ADCH – ADC Data Register
25.10.3.1 ADLAR = 0
Division Factor
32
64
128
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
25.10.3.2 ADLAR = 1
15
–
ADC7
7
R
R
0
0
14
–
ADC6
6
R
R
0
0
13
–
ADC5
5
R
R
0
0
12
–
ADC4
4
R
R
0
0
11
–
ADC3
3
R
R
0
0
10
–
ADC2
2
R
R
0
0
9
ADC9
ADC1
1
R
R
0
0
8
ADC8
ADC0
0
R
R
0
0
ADCH
ADCL
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
15
ADC9
ADC1
7
R
R
0
0
14
ADC8
ADC0
6
R
R
0
0
13
ADC7
–
5
R
R
0
0
12
ADC6
–
4
R
R
0
0
11
ADC5
–
3
R
R
0
0
10
ADC4
–
2
R
R
0
0
9
ADC3
–
1
R
R
0
0
8
ADC2
–
0
R
R
0
0
ADCH
ADCL
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
page 164.
170 ATA8742
9151A–INDCO–07/09