ATSHA204 Datasheet, PDF (17/65 Pages) ATMEL Corporation – Atmel CryptoAuthentication

Because this may affect the security of the system, it should be used with caution. See Section 8.9 and Section 8.11 for more
information about how the EEPROM seed update is controlled.
4. General I/O Information
Communications with the ATSHA204 are achieved through one of two different protocols, and selected using the part number
that is ordered:
• Single-wire Interface
This mode uses a single GPIO connection on the system microprocessor connected to SDA on the device. It permits
the fewest number of connector pins to any removable/replaceable entity. The bit rate is up to 26-Kbits/sec.
• I²C Interface
This mode is compatible with the Atmel AT24C16B Serial EEPROM interface. Two pins, Serial Data (SDA) and
Serial Clock (SCL) are required. The I²C interface supports a bit rate of up to 1Mbit/sec.
The lowest levels of the I/O protocols are described below in Sections 5 and 6. Above the I/O protocol level, however, exactly
the same bytes are transferred to and from the device to implement the cryptographic commands and error codes documented
in Section 8.
Note:
The device implements a failsafe internal watchdog timer that forces it into a very low power mode after a certain
time interval, regardless of any current activity. System programming must take this into consideration. See
Section 8.1.6 for more details.
4.1 Byte and Bit Ordering
CryptoAuthentication uses a common ordering scheme for bytes and also for the way in which numbers and arrays are
represented in this datasheet:
• All multi-byte aggregate elements are treated as arrays of bytes and are processed in the order received or
transmitted with index #0 first.
• 16-bit (2-byte) integers, typically Param2 appear on the bus least-significant byte first.
In this document, the most-significant bit or nibble of a byte or 16-bit word appears towards the left hand side of the page.
The bit order is different depending on the I/O channel used:
• On the one-wire interface, data is transferred to/from the Atmel ATSHA204 least-significant bit first on the bus.
• On the I²C interface, data is transferred to/from the Atmel ATSHA204 most-significant bit first on the bus.
4.1.1
Output Example
The following bytes will be returned in this order on the bus by a 32-byte read of the configuration section with an input
address of 0x0000:
SN[0], SN[1], SN[2], SN[3], RevNum[0], RevNum[1], RevNum[2], RevNum[3], SN[4], SN[5], SN[6], SN[7], SN[8], reserved,
I2C Enable, reserved, I2C_Address, TempOffset, OTPmode, SelectorMode, SlotConfig[0].Read, SlotConfig[0].Write,
SlotConfig[1].Read, SlotConfig[1].Write, SlotConfig[2].Read, SlotConfig[2].Write, SlotConfig[3].Read, SlotConfig[3].Write,
SlotConfig[4].Read, SlotConfig[4].Write, SlotConfig[5].Read, SlotConfig[5].Write
4.1.2
MAC Message Example
The following bytes will be passed to the SHA engine for a MAC command using a mode value of 0x71 and a KeyID of slot x.
In the example below, K[x] indicates the KeyID of slot x in the data zone, with K[0] being the first byte on the bus for a read
from or write to that slot. OTP[0] indicates the first byte on the bus for a read of the OTP zone at address zero, and so on.
K[0], K[1], K[2], K[3] … K[31], TempKey[0], TempKey[1], TempKey[2], TempKey[3] … TempKey[31], Opcode (=0x08),
Mode (=0x71), Param2(LSB = x), Param2(MSB = 0), OTP[0], OTP[1], OTP[2], OTP[3], OTP[4], OTP[5], OTP[6],
OTP[7], OTP[8], OTP[9], OTP[10], SN[8], SN[4], SN[5], SN[6], SN[7], SN[0], SN[1], SN[2], SN[3].
For more details regarding MAC messages, see Section 8.8, “MAC Command.”
Atmel ATSHA204 [DATASHEET] 17
8740D−CRYPTO−3/12