ATA5724C_14 Datasheet, PDF (17/44 Pages) ATMEL Corporation – UHF ASK/FSK Receiver

9. Data Clock
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock,
a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and bi-phase coded
signals.
9.1 Generation of the Data Clock
After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at
pin DATA. In receiving mode, the data clock control logic (Manchester/bi-phase demodulator) is active and examines the
incoming data stream. This is done, as with the bit check, by subsequent time frame checks where the distance between two
edges is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page 17, only two distances
between two edges in Manchester and bi-phase coded signals are valid (T and 2T).
The limits for T are the same as used with the bit check. They can be programmed in the LIMIT-register (Lim_min and
Lim_max, see Table 11-10 on page 25 and Table 11-11 on page 25).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Upper limit of 2T:
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
(If the result for ‘Lim_min_2T’ or ‘Lim_max_2T’ is not an integer value, it is rounded up.)
The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the
delay t_Delay after the edge on pin DATA (see Figure 9-1 on page 17).
If the data clock control logic detects a timing or logical error (Manchester code violation), as illustrated in Figure 9-2 on page
18 and Figure 9-3 on page 18, it stops the output of the data clock. The receiver remains in receiving mode and starts with
the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with
the generation of the data clock (see Figure 9-4 on page 18).
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. If the bit check is set to 0
or the receiver is set to receiving mode using the pin POLLING/_ON, the data clock is available if the data clock control logic
has detected the distance 2T (Start bit).
Note that for bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1. Timing Diagram of the Data Clock
Preburst
Data
Bit Check ok
T 2T
Dem_out
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK
Bit-check Mode
Start bit
t_Delay
t_{P_Data_Clk}
Receiving Mode,
data clock control logic active
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
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