AT91CAP9S500A Datasheet, PDF (17/52 Pages) ATMEL Corporation – Customizable Microcontroller Processor

AT91CAP9S500A/AT91CAP9S250A
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
7.3 Matrix Masters
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages twelve Masters and thus
each master can perform an access concurrently with the others, assuming that the slave it
accesses is available.
Each Master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decoding.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Master 6
Master 7
Master 8
Master 9
Master 10
Master 11
List of Bus Matrix Masters
ARM926^™ Instruction
ARM926 Data
Peripheral DMA Controller
LCD Controller
USB High Speed Device Controller
Image Sensor Interface
DMA Controller
Ethernet MAC
OHCI USB Host Controller
MP Block Master 0
MP Block Master 1
MP Block Master 2
7.4 Matrix Slaves
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages ten Slaves. Each Slave
has its own arbiter, thus permitting a different arbitration per Slave to be programmed.
17
6264AS–CAP–21-May-07