AT45DB642_14 Datasheet, PDF (17/37 Pages) ATMEL Corporation – AT45DB642_14

AC Waveforms
Waveform 1 –
Inactive Clock
Polarity Low and
SPI Mode 0
Waveform 2 –
Inactive Clock
Polarity High and
SPI Mode 3
AT45DB642
Two different timing diagrams are shown below. Waveform 1 shows the SCK/CLK signal
being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK/CLK sig-
nal being high when CS makes a high-to-low transition. Both waveforms show valid timing
diagrams. The setup and hold times for the input signals (SI or I/O7-I/O0) are referenced to the
low-to-high transition on the SCK/CLK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows
timing that is compatible with SPI Mode 3.
CS
tCSS
tWH tWL
tCSH
SCK/CLK
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE
tSU
tV
tH
tHO
VALID OUT
SI or I/O7 - I/O0
(INPUT)
VALID IN
tCS
tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO or I/O7 - I/O0
(OUTPUT)
SI or I/O7 - I/O0
(INPUT)
tCSS tWL tWH
tV
HIGH Z
tSU
tHO
VALID OUT
tH
VALID IN
tCSH
tCS
tDIS
HIGH IMPEDANCE
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