AT45CS1282 Datasheet, PDF (17/33 Pages) ATMEL Corporation – 128-megabit 2.7-volt Dual-interface Code Shadow DataFlash

AT45CS1282 [Preliminary]
AC Waveforms
Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK sig-
nal being low when CS makes a high-to-low transition, and waveform 2 shows the
SCK/CLK signal being high when CS makes a high-to-low transition. In both cases, out-
put SO becomes valid while the SCK/CLK signal is still low (SCK/CLK low time is
specified as t_WL). Timing waveforms 1 and 2 conform to RapidS serial interface but for
frequencies up to 33 MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI
Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial inter-
face. These are similar to waveform 1 and waveform 2, except that output SO is not
restricted to become valid during the t_WL period. These timing waveforms are valid over
the full frequency range (maximum frequency = 50 MHz) of the RapidS serial case.
Waveform 5 and waveform 6 are for 8-bit Rapid8 interface over the full frequency range
of operation (maximum frequency = 20 MHz).
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
t_CS
CS
SCK/CLK
t_CSS
t_WH
t_WL
t_CSH
t_V
HIGH IMPEDANCE
SO
t_HO
VALID OUT
t_DIS
HIGH IMPEDANCE
t_SU
t_H
SI
VALID IN
Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 33 MHz)
t_CS
CS
SCK/CLK
t_CSS
t_WL
t_WH
t_CSH
t_V
HIGH Z
SO
t_HO
VALID OUT
t_DIS
HIGH IMPEDANCE
t_SU
t_H
SI
VALID IN
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