AT42QT2160 Datasheet, PDF (17/49 Pages) ATMEL Corporation – QSlide™, 16-key QMatrix™ Sensor IC

AT42QT2160
5. I²C-compatible Bus Operation
5.1 Interface Bus
More detailed information about the I²C-compatible bus protocol is available from
www.i2C-bus.org. Devices are connected onto the I²C-compatible bus as shown in Figure 5-1.
Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I²C-compatible
devices must be open-drain type. This implements a wired-AND function which allows any and
all devices to drive the bus, one at a time. A low level on the bus is generated when a device
outputs a zero.
Figure 5-1. I²C-compatible Interface Bus
Vdd
Device 1 Device 2 Device 3
Device n
R1
R2
SDA
SCL
Table 5-1. I²C-compatible Bus Specifications
Parameter
Address space
Maximum bus speed (SCL)
Hold time START condition
Setup time for STOP condition
Bus free time between a STOP and START condition
Rise times on SDA and SCL
Unit
7-bit
100 kHz
4 µs minimum
4 µs minimum
4.7 µs minimum
1 µs maximum
5.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; The only exception to this rule is for
generating START and STOP conditions.
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9502A–AT42–07/08