ATTINY261_0611 Datasheet, PDF (166/236 Pages) ATMEL Corporation – 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

21.1.4
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 21-1 shows the typical pro-
gramming time for Flash accesses from the CPU.
Table 21-1. SPM Programming Time⁽¹⁾
Symbol
Min Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms
Max Programming Time
4.5 ms
Note: 1. Minimum and maximum programming time is per individual operation.
21.2 Register Description
21.2.1
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
Bit
7
6
0x37 (0x57)
–
–
Read/Write
R
R
Initial Value
0
0
5
4
3
2
1
0
–
CTPB
RFLB
PGWRT PGERS SPMEN SPMCSR
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bits 7:5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and always read as zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register. See ”EEPROM Write Prevents Writing to SPMCSR” on page 164 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
166 ATtiny261/461/861
2588B–AVR–11/06