ATMEGA128A_14 Datasheet, PDF (166/369 Pages) ATMEL Corporation – 8-bit Microcontroller with 128Kbytes

• Bit 6 – WCOL: Write COLlision flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the
SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data
Register.
• Bit 5:1 – Reserved
These bits are reserved bits in the ATmega128A and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master
mode (see Table 19-4). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is
configured as Slave, the SPI is only guaranteed to work at f_osc /4 or lower.
The SPI interface on the ATmega128A is also used for program memory and EEPROM downloading or
uploading. See page 286 for SPI Serial Programming and verification.
19.5.3 SPDR - SPI Data Register
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
SPDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Undefined
The SPI Data Register is a Read/Write Register used for data transfer between the register file and the SPI Shift
Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register
Receive buffer to be read.
ATmega 128A [DATASHEET]
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
166