ATAES132_14 Datasheet, PDF (162/171 Pages) ATMEL Corporation – 32K AES Serial EEPROM Specification

P.1.5
Read Operations
Reading beyond the end of physical memory on the AT24C32C causes the internal data address register to
roll-over to address zero. The Read operation continues from address zero.
If an ATAES132 Read operation begins at a valid User Memory address but continues past the end of User
Memory, the Read operation will not wrap to the beginning of User Memory. Reading beyond the end of User
Memory causes 0xFF to be returned to the Host in reply to the Read, the internal data address register stops
incrementing, and an error bit is set in the STATUS Register (see Appendix G.2.5, Read User Memory).
P.1.6
Read Protect
The AT24C32C and other standard I²C EEPROMs do not have a Read inhibit function.
On the ATAES132, the User Memory Read permissions are controlled by the ZoneConfig Registers (see
Appendix E.2.20, ZoneConfig Registers). The User Memory is divided into 16 user zones that are independently
controlled by 16 ZoneConfig Registers; different Read permissions can be assigned to different sections of the
memory. If Read access is prohibited, then 0xFF will be returned to the Host in reply to a Read command (see
Section 5.1, Read). By default all User Memory has open Read access.
P.1.7
Standby Mode
Standard I²C EEPROMs automatically enter low-power standby mode upon completion of any internal operation.
The ATAES132 has three powered states:
 Active State and Two Low-Power States
 Standby State
 Sleep State
The ATAES132 will remain in the Active state between operations unless the Host sends a Sleep command to
activate the Standby state or the Sleep state. The ATAES132 can also be configured to automatically enter a
Low-Power state at power-up. See Appendix L, Power Management for details on the power management
features.
P.1.8
Operating Voltage
 The AT24C32C operating range is 1.8V minimum to 5.5V maximum.
 The ATAES132 operating range is 2.5V minimum to 5.5V maximum. See Section 9.3, DC Characteristics.
P.2 SPI Serial EEPROM Compatibility
This section describes differences between the AT25320B standard Atmel 32Kb SPI Serial EEPROM and the
ATAES132 secure Serial EEPROM configured for SPI communication mode.
P.2.1
Package Pins
On the AT25320B, pin 3 is the WP input and pin 7 is the HOLD input.
On the ATAES132, pins 3 and 7 are not used in SPI communication mode; these pins can be tied to V_CC or V_SS.
The state of these two pins have no impact on the functionality of the ATAES132 in the SPI communication mode.
See Appendix K.2, SPI Communication Mode Pin Descriptions for the pin descriptions.
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ATAES132 [Datasheet]
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013