ATMEGA16HVBPRE Datasheet, PDF (160/275 Pages) ATMEL Corporation – 32 x 8 General Purpose Working Registers

ATmega16HVB/32HVB
Figure 27-6. Typical Data Transmission
SDA
Addr MSB
Addr LSB R/W
ACK
SCL
START
1
2
7
8
9
SLA+R/W
Data MSB
Data LSB ACK
1
2
7
8
9
Data Byte
STOP
27.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves
(i.e., the data being transferred on the bus must not be corrupted).
• Different masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the master with the shortest high period. The low period of the combined clock is equal to
the low period of the master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low Time-out periods when the combined
SCL line goes high or low, respectively.
Figure 27-7. SCL Synchronization between Multiple Masters
TA _low
TA _high
SCL from
Master A
SCL from
Master B
SCL bus
Line
TB _low
Masters Start
Counting Low Period
TB _high
Masters Start
Counting High Period
8042B–AVR–06/10
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