ATA6622 Datasheet, PDF (16/29 Pages) ATMEL Corporation – LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog

Figure 6-1.
VCC
3.3V/5V
Timing Sequence with R_{WD_OSC} = 51 kΩ
NRES
Undervoltage Reset
t_reset = 4 ms
t_d = 155 ms
t₁
t₁ = 20.6 ms t₂ = 21 ms
t_wd
NTRIG
Watchdog Reset
t_nres = 4 ms
t₂
t_trig > 200 ns
6.2 Worst Case Calculation with R_{WD_OSC} = 51 kΩ
The internal oscillator has a tolerance of 20%. This means that t₁ and t₂ can also vary by 20%.
The worst case calculation for the watchdog period t_wd is calculated as follows.
The ideal watchdog time t_wd is between the maximum t₁ and the minimum t₁ plus the minimum
t₂.
t_1,min = 0.8 × t₁ = 16.5 ms, t_1,max = 1.2 × t₁ = 24.8 ms
t_2,min = 0.8 × t₂ = 17.3 ms, t_2,max = 1.2 × t₂ = 26 ms
t_wdmax = t_1min + t_2min = 16.5 ms + 17.3 ms = 33.8 ms
t_wdmin = t_1max = 24.8 ms
t_wd = 29.3 ms ±4.5 ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs
correctly.
Table 6-1.
R_{WD_OSC}
kΩ
34
51
91
120
Typical Watchdog Timings
Oscillator
Period
t_osc/µs
13.3
Lead
Time
t_d/ms
105
Closed
Window
t₁/ms
14.0
19.61
154.8
20.64
33.54 264.80 35.32
42.84 338.22 45.11
Open Window
t₂/ms
14.7
21.67
37.06
47.34
Trigger Period from
Microcontroller Reset Time
t_wd/ms
t_nres/ms
19.9
4
29.32
4
50.14
4
64.05
4
16 ATA6622/ATA6624/ATA6626
4986F–AUTO–07/08