ATA3742_07 Datasheet, PDF (16/34 Pages) ATMEL Corporation – UHF ASK/FSK Receiver

Figure 5-4.
Timing Diagram for Complete Successful Bit Check
(Number of checked Bits: 3)
Bit check ok
Enable IC
Bit check
Dem_out
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Data
Startup mode
Bit check mode
Receiving mode
Figure 5-5. Timing Diagram During Bit Check
(Lim_min = 14, Lim_max = 24)
Bit check ok
Bit check ok
Enable IC
Bit check
Dem_out
Bit check
counter
T_Startup
1/2 Bit
1/2 Bit
1/2 Bit
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 1 2 3 4
T_XCLK
Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim_ < Lim_min)
Enable IC
Bit check
Dem_out
1/2 Bit
Bit check
counter
0
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 1112
0
Startup mode
Bit check mode
Sleep mode
Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim_ ≥ Lim_max)
Enable IC
Bit check
Dem_out
Bit check
counter
1/2 Bit
0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20 21 22 23 24
Start up mode
Bit check mode
0
Sleep mode
16 ATA3742
4900B–RKE–11/07