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| ATTINY10-TSHR Datasheet, PDF (151/170 Pages) ATMEL Corporation – Atmel 8-bit AVR Microcontroller | |||
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Mnemonics Operands
CBI
A, b
BST
Rr, b
BLD
Rd, b
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
LDI
Rd, K
LD
Rd, X
LD
Rd, X+
LD
Rd, - X
LD
Rd, Y
LD
Rd, Y+
LD
Rd, - Y
LD
Rd, Z
LD
Rd, Z+
LD
Rd, -Z
LDS
Rd, k
ST
X, Rr
ST
X+, Rr
ST
- X, Rr
ST
Y, Rr
ST
Y+, Rr
ST
- Y, Rr
ST
Z, Rr
ST
Z+, Rr
ST
-Z, Rr
STS
k, Rr
IN
Rd, A
OUT
A, Rr
PUSH
Rr
POP
Rd
MCU CONTROL INSTRUCTIONS
BREAK
NOP
SLEEP
WDR
Description
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twoâs Complement Overflow.
Clear Twoâs Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Copy Register
Load Immediate
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Store Direct from SRAM
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment.
Store Indirect and Pre-Decrement
Store Direct to SRAM
In from I/O Location
Out to I/O Location
Push Register on Stack
Pop Register from Stack
Break
No Operation
Sleep
Watchdog Reset
Operation
I/O(A, b) ï¬ 0
T ï¬ Rr(b)
Rd(b) ï¬ T
Cï¬1
Cï¬0
Nï¬1
Nï¬0
Zï¬1
Zï¬0
Iï¬1
Iï ï¬ 0
Sï¬1
Sï¬0
Vï¬1
Vï¬0
Tï¬1
Tï¬0
Hï¬1
Hï¬0
Rd ï¬ Rr
Rd ï¬ K
Rd ï¬ (X)
Rd ï¬ (X), X ï¬ X + 1
X ï¬ X - 1, Rd ï¬ (X)
Rd ï¬ (Y)
Rd ï¬ (Y), Y ï¬ Y + 1
Y ï¬ Y - 1, Rd ï¬ (Y)
Rd ï¬ (Z)
Rd ï¬ (Z), Z ï¬ Z+1
Z ï¬ Z - 1, Rd ï¬ (Z)
Rd ï¬ï ï¨k)
(X)ï ï¬ Rr
(X)ï ï¬ Rr, X ï¬ X + 1
X ï¬ X - 1, (X) ï¬ Rr
(Y) ï¬ Rr
(Y) ï¬ Rr, Y ï¬ Y + 1
Y ï¬ Y - 1, (Y) ï¬ Rr
(Z) ï¬ Rr
(Z) ï¬ Rr, Z ï¬ Z + 1
Z ï¬ Z - 1, (Z) ï¬ Rr
(k) ï¬ Rr
Rd ï¬ I/O (A)
I/O (A) ï¬ Rr
STACK ï¬ Rr
Rd ï¬ STACK
(see specific descr. for Break)
(see specific descr. for Sleep)
(see specific descr. for WDR)
Flags
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/2
2
2/3
1/2
2
2/3
1/2
2
2/3
1
1
1
2
1
1
2
1
1
2
1
1
1
2
2
1
1
1
1
ATtiny4/5/9/10 [DATASHEET] 151
8127FâAVRâ02/2013
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