ATA6286C_14 Datasheet, PDF (150/183 Pages) ATMEL Corporation – Embedded AVR Microcontroller with LF Receiver and UHF Transmitter

3.21.5.2 Serial Programming Algorithm
When writing serial data to the ATA6289, data is clocked on the rising edge of the SCK. When reading data from the
ATA6289, data is clocked on the falling edge of the SCK. See Figure 3-94 on page 152 for timing details. To program and
verify the ATA6289 in serial programming mode, the following sequence is recommended (see “Serial Programming
Instruction Set” in Table 3-83 on page 151):
1. Power-up sequence: Apply power between VCC and GND while RESET pin and SCK are set to “0.” In some sys-
tems, the programmer cannot guarantee that the SCK is held low during power-up. In this case, the RESET pin
must be given a positive pulse for a duration of at least two CPU clock cycles after the SCK has been set to “0.”
2. Wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to the
MOSI pin.
3. The serial programming instructions do not work if communication is out of synchronization. If in synchronization,
the second byte (0x53) echoes back when the third byte of the programming enable instruction is issued. Whether
the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET pin a positive pulse and issue a new programming enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the six
LSBs of the address and data together with the load program memory page instruction. To ensure correct loading
of the page, the data low byte must be loaded before data high byte is applied to a given address. The program
memory page is stored by loading the write program memory page instruction with the seven MSBs of the
address. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH} before issuing the next page (see
Table 3-82 on page 150). Accessing the serial programming interface before the Flash write operation is com-
pleted can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate write instruction. An EEPROM memory location is first automatically erased before new data is writ-
ten. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_EEPROM} before issuing the next byte (see
Table 3-82 on page 150). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The memory page is loaded one byte at a time by sup-
plying the six LSBs of the address and data together with the load EEPROM memory page instruction. The
EEPROM memory page is stored by loading the write EEPROM memory page instruction with the seven MSBs of
the address. When using EEPROM page access only byte locations loaded with the load EEPROM memory page
instruction are altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the user
must wait at least t_{WD_EEPROM} before issuing the next byte (see Table 3-82 on page 150). In a chip erased device,
no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the read instruction which returns the content at the selected
address at serial output MISO.
7. At the end of the programming session, the RESET pin can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET pin to “1.”
Turn VCC power off.
Table 3-82. Minimum Wait Delay Before Writing the next Flash or EEPROM Location
Symbol
t_{WD_FLASH}
t_{WD_EEPROM}
t_{WD_ERASE}
Minimum Wait Delay
4.5ms
3.6ms
9ms
150 ATA6286C [DATASHEET]
9308C–RFID–09/14