AT83SND2C_05 Datasheet, PDF (150/235 Pages) ATMEL Corporation – Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface

Interrupt
Description
As shown in Figure 101, the MMC controller implements eight interrupt sources reported
in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These
flags are detailed in the previous sections.
All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM,
F1FM, and F2EM mask bits respectively in MMMSK register.
The interrupt request is generated each time an unmasked flag is set, and the global
MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment).
This implies that register content must be saved and tested interrupt flag by interrupt
flag to be sure not to forget any interrupts.
Figure 101. MMC Controller Interrupt System
MCBI
MMINT.7
EORI
MMINT.6
EOCI
MMINT.5
EOFI
MMINT.4
F2FI
MMINT.3
F1FI
MMINT.2
F2EI
MMINT.1
F1EI
MMINT.0
MCBM
MMMSK.7
EORM
MMMSK.6
EOCM
MMMSK.5
EOFM
MMMSK.4
F2FM
MMMSK.3
F1FM
MMMSK.2
F2EM
MMMSK.1
F1EM
MMMSK.0
EMMC
IEN1.0
MMC Interface
Interrupt Request
150 AT8xC51SND2C
4341D–MP3–04/05