ATTINY15L-1SU Datasheet, PDF (15/85 Pages) ATMEL Corporation – 8-bit Microcontroller with 1K Byte Flash

Power-on Reset
1187H–AVR–09/07
ATtiny15L
Table 5. Reset Delay Selections⁽¹⁾
BODEN⁽²⁾
x
x
x
1
0
CKSEL [1:0]⁽²⁾
00
01
10
11
11
Start-up Time,
t_TOUT at V_CC = 2.7V
256 ms + 18 CK
256 ms + 18 CK
16 ms + 18 CK
18 CK + 32 µs
18 CK + 128 µs
Start-up Time,
t_TOUT at V_CC = 5.0V
64 ms + 18 CK
64 ms + 18 CK
4 ms + 18 CK
18 CK + 8 µs
18 CK + 32 µs
Recommended
Usage
BOD disabled,
slowly rising
power
BOD disabled,
slowly rising
power
BOD disabled,
quickly rising
power
BOD disabled
BOD enabled
Notes: 1. On Power-up, the start-up time is increased with typical 0.6 ms.
2. “0” means programmed, “1” means unprogrammed.
Table 5 shows the start-up times from Reset. When the CPU wakes up from Power-
down, only the clock-counting part of the start-up time is used. The Watchdog Oscillator
is used for timing the real-time part of the start-up time. The number Watchdog Oscilla-
tor cycles used for each time-out is shown in Table 6.
The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electri-
cal Characteristics section on page 64. The device is shipped with CKSEL = “00”.
Table 6. Number of Watchdog Oscillator Cycles
V_CC Conditions
2.7V
Time-out
32 µs
2.7V
128 µs
2.7V
16 ms
2.7V
256 ms
5.0V
8 µs
5.0V
32 µs
5.0V
4 ms
5.0V
64 ms
Number of Cycles
8
32
4K
64K
8
32
4K
64K
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is nominally defined in Table 4. The POR is activated whenever V_CC is below
the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay, for which the device is kept in RESET after V_CC rise. The Time-out
period of the delay counter can be defined by the user through the CKSEL Fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
activated again, without any delay, when the V_CC decreases below detection level.
15