ATMEGA165PV_14 Datasheet, PDF (148/364 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega165P
17. SPI – Serial Peripheral Interface
17.1 Features
17.2 Overview
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega165P and peripheral devices or between several AVR devices.
The PRSPI bit in “PRR – Power Reduction Register” on page 41 must be written to zero to
enable SPI module.
Figure 17-1. SPI Block Diagram⁽¹⁾
DIVIDER
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8019K–AVR–11/10
Note: 1. Refer to Figure 1-1 on page 2, and Table 12-3 on page 69 for SPI pin placement.
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