AT89C51RE2 Datasheet, PDF (146/187 Pages) ATMEL Corporation – 8-bit Flash Microcontroller

Registers
Table 107. SSCON Register
SSCON - Synchronous Serial Control register (93h)
7
6
5
4
3
2
1
0
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
Bit
Bit
Number Mnemonic Description
7
CR2
Control Rate bit 2
See Table 101.
Synchronous Serial Interface Enable bit
6
SSIE Clear to disable the TWI module.
Set to enable the TWI module.
5
STA
Start flag
Set to send a START condition on the bus.
4
ST0
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
3
SI
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
2
AA Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
1
CR1
Control Rate bit 1
See Table 101.
0
CR0
Control Rate bit 0
See Table 101.
Table 108. SSDAT (95h) - Syncrhonous Serial Data register (read/write)
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
7
6
5
4
3
2
1
0
Bit
Bit
Number Mnemonic Description
7
SD7 Address bit 7 or Data bit 7.
6
SD6 Address bit 6 or Data bit 6.
5
SD5 Address bit 5 or Data bit 5.
4
SD4 Address bit 4 or Data bit 4.
3
SD3 Address bit 3 or Data bit 3.
2
SD2 Address bit 2 or Data bit 2.
146 AT89C51RE2
7663D–8051–10/08