ATTINY20_11 Datasheet, PDF (143/224 Pages) ATMEL Corporation – 8-bit Microcontroller with 2K Bytes In-System Programmable Flash

ATtiny20
17.3.8
Arbitration
In the case where the slave is stretching the clock the master will be forced into a wait-state until
the slave is ready and vice versa.
A master can only start a bus transaction if it has detected that the bus is idle. As the TWI bus is
a multi master bus, it is possible that two devices initiate a transaction at the same time. This
results in multiple masters owning the bus simultaneously. This is solved using an arbitration
scheme where the master loses control of the bus if it is not able to transmit a high level on the
SDA line. The masters who lose arbitration must then wait until the bus becomes idle (i.e. wait
for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not
involved in the arbitration procedure.
Figure 17-9. TWI Arbitration
Figure 17-9 shows an example where two TWI masters are contending for bus ownership. Both
devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to
transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data
bit, or a repeated START condition and STOP condition are not allowed and will require special
handling by software.
17.3.9
Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one mas-
ter is trying to control the SCL line at the same time. The algorithm is based on the same
principles used for clock stretching previously described. Figure 17-10 shows an example where
two masters are competing for the control over the bus clock. The SCL line is the wired-AND
result of the two masters clock outputs.
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