ATMEGA48P_14 Datasheet, PDF (14/420 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
15
SP15
SP7
7
R/W
R/W
RAMEND
RAMEND
14
SP14
SP6
6
R/W
R/W
RAMEND
RAMEND
13
SP13
SP5
5
R/W
R/W
RAMEND
RAMEND
12
SP12
SP4
4
R/W
R/W
RAMEND
RAMEND
11
SP11
SP3
3
R/W
R/W
RAMEND
RAMEND
10
SP10
SP2
2
R/W
R/W
RAMEND
RAMEND
9
SP9
SP1
1
R/W
R/W
RAMEND
RAMEND
8
SP8
SP0
0
R/W
R/W
RAMEND
RAMEND
SPH
SPL
7.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clk_CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7-5. Single Cycle ALU Operation
T1
T2
T3
T4
clk_CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
14 ATmega48P/88P/168P
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