ATA5743 Datasheet, PDF (14/43 Pages) ATMEL Corporation – UHF ASK/FSK Receiver

Figure 6-3. Timing Diagram for Complete Successful Bit Check
(Number of checked Bits: 3)
Bit check ok
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
T_Start-up
Start-up mode
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
T_Bit-check
Bit-check mode
Receiving mode
6.3.1
6.3.2
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter, and signals due to noise. This is done by subsequent time
frame checks where the distances between two signal edges are continuously compared to a
programmable time window. The maximum count of this edge-to-edge test before the receiver
switches to receiving mode is also programmable.
Configuring the Bit Check
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maxi-
mum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N_Bit-check in the
OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If N_Bit-check is
set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if N_Bit-check is set to a lower
value. In polling mode, the bit-check time is not dependent on N_Bit-check. Figure 6-3 shows an
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
As demonstrated in Figure 6-4, the time window for the bit check is defined by two separate time
limits. If the edge-to-edge time t_ee is between the lower bit-check limit, T_{Lim_min}, and the upper
bit-check limit, T_{Lim_max}, the check will be continued. If t_ee is smaller than T_{Lim_min}, or t_ee exceeds
T_{Lim_max}, the bit check will be terminated and the receiver will switch to sleep mode.
Figure 6-4. Valid Time Window for Bit Check
1/f_Sig
Dem_out
t_ee
T_{Lim_min}
T_{Lim_max}
For best noise immunity it is recommended to use a low span between T_{Lim_min} and T_{Lim_max}.
This is achieved by using a fixed frequency at a 50% duty cycle for the transmitter preburst. For
this reason, a “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t_ee. Using preburst patterns that contain
various edge-to-edge time periods, the bit-check limits must be programmed according to the
required span.
14 ATA5743
4839B–RKE–08/05