AT88SC1608_14 Datasheet, PDF (14/24 Pages) ATMEL Corporation – High Security Memory Including Anti-wiretapping

11.4
Acknowledge
All addresses and data are serially transmitted to and from the device in 8-bit words. The device
sends a zero to acknowledge that it has received each byte. This happens during the ninth clock
cycle. During read operations, the host must pull the SDA line low during the ninth clock cycle to
acknowledge that it has received the data byte. Failure to transmit this ACK bit will terminate the
read operation.
11.5
Standby Mode
The AT88SC1608 features a low-power standby mode that is enabled upon power-up and after
the receipt of the stop bit and the completion of any internal operations.
11.6
Acknowledge Polling
Once the internally-timed write cycle has started and the device inputs are disabled, acknowl-
edge polling can be initiated. This involves sending a start condition followed by the device
address representative of the operation desired. Only if the internal write cycle has completed
will the device respond with a “0”, allowing the sequence to continue.
Figure 11-1. Start and Stop Definition
Note: The SCL input should be low when the device is idle. Therefore, SCL is low before a start condi-
tion and after a stop condition.
Figure 11-2. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
14 AT88SC1608
0971H–SMEM–6/08