AT45DB321C Datasheet, PDF (14/37 Pages) ATMEL Corporation – 32 MEGABIT 2.7 VOLT DATAFLASH

Time
Period
1
2
3
WP Pin
High
High
High
Low
High
High
High
Enable Sector Protection Command
Command Not Issued Previously
Command Issued
–
x
Command Issued during Period 1 or 2
–
Issue Command
Disable Sector Protection Command
x
–
Command Issued
x
Not Issued Yet
Command Issued
–
Sector Protection Status
Disabled
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. The RESET pin is also internally pulled
high; therefore, in low pin count applications, connection of the RESET pin is not neces-
sary if this pin and feature will not be utilized. However, it is recommended that the
RESET pin be driven high externally whenever possible.
READY/BUSY: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed. During
Page Erase and Block Erase, read and write operations can be performed to both
buffers.
14 AT45DB321C [Preliminary]
3387B–DFLSH–9/04