ATTINY24_14 Datasheet, PDF (137/238 Pages) ATMEL Corporation – High Performance, Low Power AVR

ATtiny24/44/84
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 16-6 below. This assures a fixed delay from the trigger event to the start of conversion. In
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
2
3
4
5
6
7
8
9
10 11 12 13
12
MUX and REFS
Update
Sample &
Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
Prescaler
Reset
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See Figure 16-7.
Figure 16-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
Cycle Number ^{12 13 14 1}
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Conversion
Complete
Sample & Hold
MUX and REFS
Update
8006K–AVR–10/10
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