ATMEGA128L_14 Datasheet, PDF (134/386 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega128
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 61. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 123.)
Table 61. Waveform Generation Mode Bit Description
WGMn2 WGMn1 WGMn0
Mode WGMn3 (CTCn) (PWMn1) (PWMn0)
Timer/Counter Mode of
Operation⁽¹⁾
TOP
Update of
OCRnx at
TOVn Flag
Set on
0
0
0
0
0
Normal
0xFFFF Immediate MAX
1
0
0
0
1
PWM, Phase Correct, 8-bit
0x00FF TOP
BOTTOM
2
0
0
1
0
PWM, Phase Correct, 9-bit
0x01FF TOP
BOTTOM
3
0
0
1
1
PWM, Phase Correct, 10-bit 0x03FF TOP
BOTTOM
4
0
1
0
0
CTC
OCRnA Immediate MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF BOTTOM
TOP
6
0
1
1
0
Fast PWM, 9-bit
0x01FF BOTTOM
TOP
7
0
1
1
1
Fast PWM, 10-bit
0x03FF BOTTOM
TOP
8
1
0
0
0
PWM, Phase and Frequency
Correct
ICRn
BOTTOM
BOTTOM
9
1
0
0
1
PWM, Phase and Frequency
Correct
OCRnA BOTTOM
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICRn
TOP
BOTTOM
11
1
0
1
1
PWM, Phase Correct
OCRnA TOP
BOTTOM
12
1
1
0
0
CTC
ICRn
Immediate MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICRn
BOTTOM
TOP
15
Note:
1
1
1
1
Fast PWM
OCRnA BOTTOM
TOP
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
2467X–AVR–06/11
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