AT91R40807_14 Datasheet, PDF (131/153 Pages) ATMEL Corporation – Fully Programmable External Bus Interface

AT91X40 Series
TC User Interface
TC Base Address: 0xFFFE0000 (Code Label TC_BASE)
Table 16. TC Global Memory Map
Offset
Channel/Register
0x00
TC Channel 0
0x40
TC Channel 1
0x80
TC Channel 2
0xC0
TC Block Control Register
0xC4
TC Block Mode Register
Name
TC_BCR
TC_BMR
Access
See Table 17
See Table 17
See Table 17
Write Only
Read/Write
Reset State
–
0
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 17. The offset of each of the Channel registers in Table 17 is in relation to the offset of the
corresponding channel as mentioned in Table 16.
Table 17. TC Channel Memory Map
Offset
Register
0x00
Channel Control Register
0x04
Channel Mode Register
0x08
Reserved
0x0C
Reserved
0x10
Counter Value
0x14
Register A
0x18
Register B
0x1C
Register C
0x20
Status Register
0x24
Interrupt Enable Register
0x28
Interrupt Disable Register
0x2C
Interrupt Mask Register
Note: Read Only if WAVE = 0
Name
TC_CCR
TC_CMR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
TC_IER
TC_IDR
TC_IMR
Access
Write Only
Read/Write
Read/Write
Read/Write⁽¹⁾
Read/Write⁽¹⁾
Read/Write
Read Only
Write Only
Write Only
Read Only
Reset State
–
0
–
–
0
0
0
0
0
–
–
0
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