ATTINY40_14 Datasheet, PDF (130/204 Pages) ATMEL Corporation – 8-bit Atmel tinyAVR Microcontroller

17.5 Register Description
17.5.1
TWSCRA – TWI Slave Control Register A
Bit
0x2D
Read/Write
Initial Value
7
6
TWSHE
–
R/W
R
0
0
5
TWDIE
R/W
0
4
TWASIE
R/W
0
3
TWEN
R/W
0
2
TWSIE
R/W
0
1
TWPME
R/W
0
0
TWSME
R/W
0
TWSCRA
• Bit 7 – TWSHE: TWI SDA Hold Time Enable
When this bit is set each negative transition of SCL triggers an additional internal delay, before the device is
allowed to change the SDA line. The added delay is approximately 50ns in length.
This may be useful in SMBus systems.
• Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 5 – TWDIE: TWI Data Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the data interrupt flag
(TWDIF) in TWSSRA is set.
• Bit 4 – TWASIE: TWI Address/Stop Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the address/stop interrupt
flag (TWASIF) in TWSSRA is set.
• Bit 3 – TWEN: Two-Wire Interface Enable
When this bit is set the slave Two-Wire Interface is enabled.
• Bit 2 – TWSIE: TWI Stop Interrupt Enable
Setting the Stop Interrupt Enable (TWSIE) bit will set the TWASIF in the TWSSRA register when a STOP condition
is detected.
• Bit 1 – TWPME: TWI Promiscuous Mode Enable
When this bit is set the address match logic of the slave TWI responds to all received addresses. When this bit is
cleared the address match logic uses the TWSA register to determine which address to recognize as its own.
• Bit 0 – TWSME: TWI Smart Mode Enable
When this bit is set the TWI slave enters Smart Mode, where the Acknowledge Action is sent immediately after the
TWI data register (TWSD) has been read. Acknowledge Action is defined by the TWAA bit in TWSCRB.
When this bit is cleared the Acknowledge Action is sent after TWCMDn bits in TWSCRB are written to 1X.
17.5.2 TWSCRB – TWI Slave Control Register B
Bit
0x2C
Read/Write
Initial Value
7
6
5
4
–
–
–
–
R
R
R
R
0
0
0
0
3
2
1
0
–
TWAA TWCMD1 TWCMD0 TWSCRB
R
R/W
W
W
0
0
0
0
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read as zero.
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
130